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MDT2060
1. General Description
This EPROM-Based 8-bit micro-controller uses a fully static CMOS technology process to achieve higher speed and smaller size with the low power u 4 types of oscillator can be selected by programming option: RCLow cost RC oscillator LFXTLow frequency crystal oscillator XTALStandard crystal oscillator HFXTHigh frequency crystal oscillator
consump-tion and high noise immunity. On chip memory incl-udes 1K words of ROM, and 36 bytes of static RAM.
2. Features
The followings are some of the features on the hardware and software : u u u u Fully CMOS static design 8-bit data bus On chip EPROM size : 1.0 K words Internal RAM size : 49 bytes (36 general purpose registers, 13 special registers) u u u u u u u 37 single word instructions 14-bit instructions 8-level stacks Operating voltage : 2.5 V ~ 5.5 V (PRD Disable) 4.5 V ~ 5.5 V (PRD Enable) Operating frequency : DC ~ 20 MHz The most fast execution time is 200 ns under 20 MHz in all single cycle instructions except the branch instruction u u u u u u Addressing modes include direct, indirect and relative addressing modes Power-on Reset Power edge-detector Reset Power range-detector Reset Sleep Mode for power saving 3 interrupt sources: -External INT pin -TMR0 timer -PortB<7:4> interrupt on change
u u u
8-bit real time clock/counter(RTCC) with 8-bit programmable prescaler On-chip RC oscillator based Watchdog Timer(WDT) 13 I/O pins with their own independent direction control
3. Applications
The application areas of this MDT2060 range from appliance motor control and high speed automotive to low power remote transmitters/receivers, pointing devices, and telecommunications processors, such as Remote controller, small instruments, chargers, toy, automobile and PC peripheral ... etc.
4. Pin Assignment PA2 1 PA3 2 PA4/RTCC 3 /MCLR 4 Vss 5 PB0/INT 6 PB1 7 PB2 8 PB3 9 18 17 16 15 14 13 12 11 10 PA1 PA0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 1
2004/1
Ver. 1.6
MDT2060
5. Pin Function Description
Pin Name PA0~PA3 PB0~PB7 I/O I/O I/O Port A, TTL input level Port B, TTL input level / PB0:External interrupt input , PB4~PB7:Interrupt on pin change RTCC/PA4 I/O Real Time Clock/Counter, Schmitt Trigger input levels Open drain output /MCLR OSC1 OSC2 Vdd Vss I I O Master Clear, Schmitt Trigger input levels Oscillator Input Oscillator Output Power supply Ground Function Description
6. Memory Map (A) Register Map
Address BANK0 00 01 02 03 04 05 06 0A 0B 0C~2F BANK1 01 05 06 07 TMR CPIO A CPIO B PSTA Indirect Addressing Register RTCC PCL STATUS MSR Port A Port B PCH INTS General purpose register Description
(1) IAR ( Indirect Address Register) : R00 This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 2
2004/1
Ver. 1.6
MDT2060
(2) RTCC (Real Time Counter/Counter Register) : R01 (3) PC (Program Counter) : R02,R0A Write PC --- from PCH LJUMP, LCALL --- from instruction word RTIW, RET,RTFI --- from STACK
A9
A8
A7~A0
Write PC --- from ALU LJUMP, LCALL --- from instruction word RTIW, RET, RTFI --- from STACK
(4) STATUS (Status register) : R03
Bit
0 1 2 3 4 5
Symbol
C HC Z PF TF RBS0 Carry bit Half Carry bit Zero bit
Function
Power down Flag bit WDT Timer overflow Flag bit Register Bank Select bit : 0 : 00H --- 7FH 1 : 80H --- FFH
7~6
XX
General purpose bit
(5) MSR (Memory Bank Select Register) : R4 Memory Bank Select Register : 0 : 00~7F 1 : 80~FF
b7
b6
b5
b4
b3
b2
b1
b0
Indirect Addressing Mode
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 3
2004/1
Ver. 1.6
MDT2060
(6) PORT A : R05 PA4~PA0, I/O Register (7) PORT B : R06 PB7~PB0, I/O Register (8)PCH (High byte of PC) : R0A
Bit 1~0 7~2
Function High byte of PC Unimplemented, reads as0|
(9) INTS ( Interrupt Status Register ) : R0B
Bit 0 1 2 3
Symbol RBIF INTF TIF RBIE
Function PORT B change interrupt flag. Set when PB <7:4> inputs change Set when INT interrupt occurs. INT interrupt flag. Set when TMR overflows. 0 : disable PB change interrupt 1 : enable PB change interrupt
4
INTS
0 : disable INT interrupt 1 : enable INT interrupt
5
TIS
0 : disable TMR interrupt 1 : enable TMR interrupt
6 7
-GIS
Unimplemented 0 : disable global interrupt 1 : enable global interrupt
(10) TMR (Time Mode Register) : R81 Bit Symbol Prescaler Value 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Function RTCC rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
2X0
PS2X0
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 4
2004/1
Ver. 1.6
MDT2060
Bit 3 Symbol PSC Function Prescaler assignment bit : 0 X RTCC 1 X Watchdog Timer RTCC signal Edge : 0 X Increment on low-to-high transition on RTCC pin 1 X Increment on high-to-low transition on RTCC pin RTCC signal set : 0 X Internal instruction cycle clock 1 X Transition on RTCC pin Interrupt edge select 0 X Interrupt on falling edge on PB0 1 X Interrupt on rising edge on PB0 PORTB pull-hi 0 X PORTB pull-hi are enable 1 X PORTB pull-hi are disable
4
TCE
5
TCS
6
IES
7
PBPH
(11) CPIO A (Control Port I/O Mode Register) : R85 x"0", I/O pin in output mode; x"1", I/O pin in input mode. (12) CPIO B (Control Port I/O Mode Register) : R86 x"0", I/O pin in output mode; x"1", I/O pin in input mode. (13) PSTA : R87 Bit 0 1 Symbol PRDB PORB Function 0:Power range-detector Reset occurred 1:No Power range-detector Reset Occurred 0:Power on Reset occurred 1:No Power on Reset occurred
(14) Configurable options for EPROM (Set by writer) : Oscillator Type RC Oscillator
HFXT Oscillator XTAL Oscillator LFXT Oscillator
Watchdog Timer control Watchdog timer disable all the time Watchdog timer enable all the time This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 5
2004/1
Ver. 1.6
MDT2060
Power-range control Power-range disable Power-range enable
Oscillator-start Timer control 0ms 80ms
Power-edge Detect PED Disable PED Enable
Security state Security weak Disable Security Disable Security Enable
The default security state of EPROM is weak disable. Once the IC was set to enable or disable, it's forbidden to change. (B) Program Memory Address 000-3FF 000 004 Program memory The starting address of power on, external reset or WDT time-out reset. Interrupt vector Description
7. Reset Condition for all Registers
Power-On Reset, Power range detector Reset xxxx xxxx 00 0000 0000 0001 1xxx xxxx xxxx - - -1 xxxx xxxx xxxx 0000 0001 1111 1111
Register IAR RTCC PC STATUS MSR PORT A PORT B INTS TMR
Address 00h 01h 0Ah,02h 03h 04h 05h 06h 0Bh 81h
/MCLR or WDT Reset uuuu uuuu 00 0000 0000 000# #uuu uuuu uuuu - - -1 uuuu uuuu uuuu 0000 000u 1111 1111
Wake-up from SLEEP uuuu uuuu 00 0000 0100 000# #uuu uuuu uuuu - - -u uuuu uuuu uuuu uuuu uuuu uuuu uuuu
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 6
2004/1
Ver. 1.6
MDT2060
Register CPIOA CPIOB PSTA Address 85h 86h 87h Power-On Reset, Power range detector Reset - - -1 1111 1111 1111 - - - - - -qq /MCLR or WDT Reset - - -1 1111 1111 1111 - - - - - -uu Wake-up from SLEEP - - -u uuuu uuuu uuuu - - - - --uu
Note : uxunchanged, x xunknown, - xunimplemented, read as "0" #xvalue depends on the condition of the following table
Condition /MCLR reset (not during SLEEP) /MCLR reset during SLEEP WDT reset (not during SLEEP) WDT reset during SLEEP Power on reset Power range-detector Reset
Status: bit 4 u 1 0 0 1 1
Status: bit 3 u 0 1 0 1 1
Status: bit 1 1 1 1 1 0 1
Status: bit 0 1 1 1 1 X 0
8. Instruction Set :
Instruction Code 010000 00000000 010000 00000001 010000 00000010 010000 00000011 010000 00000100 010000 00000rrr 010001 1rrrrrrr 011000 trrrrrrr 111010 iiiiiiii 010111 trrrrrrr 011001 trrrrrrr 011010 trrrrrrr 011011 trrrrrrr 011100 trrrrrrr 011101 trrrrrrr 011110 trrrrrrr Mnemonic Operands NOP CLRWT SLEEP TMODE RET CPIO R STWR R LDR R, t LDWI I SWAPR R, t INCR R, t INCRSZ R, t ADDWR R, t SUBWR R, t DECR R, t DECRSZ R, t No operation Clear Watchdog timer Sleep mode Load W to TMODE register Return from subroutine Control I/O port register Store W to register Load register Load immediate to W Swap halves register Increment register Increment register, skip if zero Add W and register Subtract W from register Decrement register Decrement register, skip if zero Function Operating None 0/WT 0/WT, stop OSC W/TMODE Stack/PC W/CPIO r W/R R/t I/W [R(0~3) R(4~7)] /t R + 1/t R + 1/t W + R/t R W/t or (R+/W+1/t) R 1/t R 1/t TF, PF TF, PF None None None None Z None None Z None C, HC, Z C, HC, Z Z None Status
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 7
2004/1
Ver. 1.6
MDT2060
Instruction Code 010010 trrrrrrr 110100 iiiiiiii 010011 trrrrrrr 110101 iiiiiiii 010100 trrrrrrr 110110 iiiiiiii 011111 trrrrrrr 010110 trrrrrrr 010101 trrrrrrr 010000 1xxxxxxx 010001 0rrrrrrr 0000bb brrrrrrr 0010bb brrrrrrr 0001bb brrrrrrr 0011bb brrrrrrr 100nnn nnnnnnnn 101nnn nnnnnnnn 110111 iiiiiiii 110001 iiiiiiii 111000 iiiiiiii 010000 00001001 Note : W WT TMODE CPIO TF PF PC OSC Inclu. Exclu. AND : : : : : : : : : : : Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter Oscillator Inclusive ` a' Exclusive ` o' Logic AND ` a' b t : : 0 1 R : C : HC : Z : / : x : i : n : Bit position Target : Working register : General register General register address Carry flag Half carry Zero flag Complement Don't care Immediate data ( 8 bits ) Immediate address Mnemonic Operands ANDWR R, t ANDWI i IORWR R, t IORWI i XORWR R, t XORWI i COMR R, t RRR RLR CLRW CLRR BCR BSR R R, b R, b R, t R, t Function AND W and register AND W and immediate Inclu. OR W and register Inclu. OR W and immediate Exclu. OR W and register Exclu. OR W and immediate Complement register Rotate right register Rotate left register Clear working register Clear register Bit clear Bit set Bit Test, skip if clear Bit Test, skip if set Long CALL subroutine Long JUMP to address Add immediate to W Return, place immediate to W Subtract W from immediate Reture from interrupt Operating R a W/t i a W/W R a W/t i a W/W R o W/t i o W/W /R/t R(n) /R(n-1), C/R(7), R(0)/C R(n)/r(n+1), C/R(0), R(7)/C 0/W 0/R 0/R(b) 1/R(b) Skip if R(b)=0 Skip if R(b)=1 n/PC, PC+1/Stack LJUMP n ADDWI i RTIW i n/PC W+i/W Stack/PC,i/W i-W/W Stack/PC,1/GIS None C,HC,Z None C,HC,Z None Z Z None None None None None C Status Z Z Z Z Z Z Z C
BTSC R, b BTSS R, b LCALL n
SUBWI i RTFI
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 8
2004/1
Ver. 1.6
MDT2060
9. Electrical Characteristics
*Note: Temperature=25C 1.Operation Current : (1) HF (C=10p) , WDT - enable, PRD - disable SleepAWDT-disableA 4M 2.5V 3.0V 4.0V 5.0V 6.4V 200u 300u 530u 800u 1.4m 10M 500u 680u 1.0m 1.5m 2.5m 20M 900u 1.1m 1.7m 2.5m 3.8m Sleep 1u 3u 8u 20u 45u PRD-disable 1u 1u 1u 1u 1u
(2) XT (C=10p) , WDT - enable, PRD - disable SleepAWDT-disableA 1M 2.5V 3.0V 4.0V 5.0V 6.4V 50u 100u 220u 400u 720u 4M 150u 280u 500u 800u 1.3m 10M 300u 550u 1m 1.3m 2.1m Sleep 1u 3u 8u 20u 45u PRD-disable 1u 1u 1u 1u 1u
(3) RC, WDT - Enable; PRD - Disable; @Vdd = 5.0V SleepAWDT-disableA C R 4.7k 10k 3p 47k 100k 300k 470k 4.7k 10k 20p 47k 100k 300k 470k Freq. 12.4M 6.3M 1.42M 715K 235K 146K 5.8M 2.9M 660K 318K 105K 66K Current 1.6m 900u 250u 160u 110u 90u 900u 500u 180u 120u 90u 85u PRD-disable 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 9
2004/1
Ver. 1.6
MDT2060
SleepAWDT-disableA C R 4.7k 10k 100p 47k 100k 300k 470k 4.7k 10k 300p 47k 100k 300k 470k Freq. 1.75M 880K 190K 92K 31K 19K 800K 380K 83K 39K 13K 8K Current 320u 200u 110u 95u 90u 85u 180u 130u 100u 95u 90u 85u PRD-disable 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u
(4) LF (C=10p) , WDT - disable, PRD - disable, 32K 2.5V 3.0V 4.0V 5.0V 6.4V 5u 6u 12u 30u 130u 455K 35u 40u 65u 100u 165u 1M 50u 70u 110u 150u 250u Sleep 1u 1u 1u 1u 1u
2. Input Voltage (Vdd = 5V) : Port Vil TTL Schmitt trigger Vih TTL Schmitt trigger Min Vss Vss 2.2V 3.5V Max 1.0V 0.6V Vdd Vdd
3. Output Voltage (Vdd = 5V) : PA,PB Voh Vol Voh Vol 4.0V 0.7V 4.4V 0.3v Condition Ioh = -20mA Iol = 20mA Ioh = -5mA Iol = 5mA
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 10
2004/1
Ver. 1.6
MDT2060
4. Output Current (Max.) (Vdd = 5V) : Port A: source current sink current Current 30mA 50mA
Port B: source current sink current
Current 30mA 50mA
5. The basic WDT time-out cycle time : Time 2.5V 3.0V 4.0V 5.0V 6.3V 25 23 20 18 16 Unit = ms
6. PRD : (1)PRD reset voltage : Voltage Vh Vl 4.05% 3.65% Unit = V (2) PRD reset current : Current 4.0V 3.6V 100 80 Unit = uA 7. Min Operation Voltage : C => XT, 20M HF, 20M 10p 2.5 2.5 20p 3.0 2.8 30p 3.3 3.0 Unit = V
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 11
2004/1
Ver. 1.6
MDT2060
RC, 1k, no cap. 2.5 Unit = V C => LF, 1M 0p 2.5 10p 2.5 20p 2.5 Unit = V
8. MCLR filter time : Vdd=5V time 720 Unit = ns
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 12
2004/1
Ver. 1.6

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